1. Field of the Invention
The present invention relates to a selector circuit for selecting a desired image area of and to an image pickup apparatus using the selector circuit.
2. Related Background Art
With a conventional image sensor having a plurality of solid image pickup elements disposed in a two-dimensional X-Y coordinate plane, each pixel can be directly accessed and a predetermined pixel area can be designated by using horizontal and vertical shift registers for designating X- and Y-addresses and decoder circuits for controlling the horizontal and vertical shift registers.
The number of pixels of a recent image pickup apparatus using solid state image pickup elements is increasing year after year, and for this reason, the number of bits of a decoder increases and the circuit structure becomes complicated. For example, a solid state image pickup device having 2000 pixels in the horizontal line requires a decoder circuit of 11 bits or 211=2024 in order to select each of 2000 pixels.
If all pixels are to be randomly accessed without using a decoder circuit, a pixel area not to be accessed is skipped at high speed, according to conventional techniques. This method is, however, associated with a problem of a large power consumption to be caused by a high speed operation. In order to solve this problem, a shift register of a memory type has been proposed.
Such the shift register is disclosed, for example, in Japanese Patent Application Laid-Open No. 6-350933, in which each shift register unit is provided with a potential storage unit so that pixels in a desired pixel area can be read. FIG. 1 is a diagram showing the outline of that shift register. In FIG. 1, a shift register unit block 104 is constituted of a shift register unit 101, a storage unit 103 and a switch 102. The shift register unit 101 is constituted of two serially connected inverters 105 and 106. The storage unit 103 stores information of the shift register unit 101. The switch 102 transfers the information stored in the storage unit 103 to the shift register unit 101. A plurality of unit blocks 104 are connected in cascade to constitute the shift register. Image data of each unit block stored in the storage unit 103 is sequentially read on a unit block basis to read necessary image data. However, this requires a two-step process including a process for setting a read-out start position and a process for reading out a desired area.